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Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADN8831
ILIMC
1
24
COMPSW
IN1P
IN1N
OUT1
IN2P
IN2N
OUT2
VREF
2
3
4
5
6
7
8
PIN 1
INDICATOR
ADN8831
TOP VIEW
(Not to Scale)
23
22
21
20
19
18
17
SFB
PGND
SNGATE
SW
SPGATE
PVDD
COMPOSC
NOTES
1. THE LFCSP PACKAGE HAS AN EXPOSED PADDLE
THAT SHOULD BE CONNECTED TO AGND (PIN 12)
AND THE ASSOCIATED PCB GROUND PLANE.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
ILIMC
IN1P
IN1N
OUT1
IN2P
IN2N
OUT2
VREF
AVDD
PHASE
TMPGD
AGND
FREQ
SS/SB
Type
Analog Input
Analog Input
Analog Input
Analog Output
Analog Input
Analog Input
Analog Output
Analog Output
Power
Analog Input
Digital Output
Ground
Analog Input
Analog Input
Description
Sets TEC Cooling Current Limit.
Noninverting Input to Error Amplifier.
Inverting Input to Error Amplifier.
Output of Error Amplifier.
Noninverting Input to Compensation Amplifier.
Inverting Input to Compensation Amplifier.
Output of Compensation Amplifier.
2.5 V Voltage Reference Output.
Power for Nondriver Sections. 3.0 V minimum; 5.5 V maximum.
Sets SYNCO Clock Phase Relative to SYNCI/SD Clock.
Logic Output. Active high. Indicates when the OUT1 voltage is within ±100 mV of IN2P voltage.
Analog Ground. Connect to low noise ground.
Sets Switching Frequency with an External Resistor.
Sets Soft Start Time for Output Voltage. Pull low (VTEC = 0 V) to put the ADN8831 into standby
mode.
15
SYNCO
Digital Output
Phase Adjustment Clock Output. Phase set from PHASE pin. Used to drive SYNCI/SD of other
ADN8831 devices.
16
SYNCI/SD
Digital Input
Optional Clock Input. If not connected, clock frequency is set by FREQ pin. Pull low to put
the ADN8831 into shutdown mode. Pull high to negate shutdown mode.
17
COMPOSC
Analog Output
Compensation for Oscillator. Connect to PVDD when in free-run mode, connect to R-C
network when in external clock mode.
18
19
20
21
22
23
24
25
26
27
28
29
PVDD
SPGATE
SW
SNGATE
PGND
SFB
COMPSW
LPGATE
LNGATE
LFB
CS
ITEC
Power
Analog Output
Analog Input
Analog Output
Ground
Analog Input
Analog Input
Analog Output
Analog Output
Analog Input
Analog Input
Analog Output
Power for Output Driver Sections. 3.0 V minimum; 5.5 V maximum.
PWM Output Drives External PMOS Gate.
Connects to PWM FET Drains.
PWM Output Drives External NMOS Gate.
Power Ground. External NMOS devices connect to PGND. Connect to digital ground.
PWM Feedback. Connect to the TEC module negative (?) terminal.
Compensation Pin for Switching Amplifier.
Linear Output Drives External PMOS Gate.
Linear Output Drives External NMOS Gate.
Linear Feedback. Connect to H-Bridge transistor output and current sense resistor.
Linear Feedback. Connect to the TEC module positive (+) terminal.
Indicates TEC Current.
Rev. A | Page 7 of 20
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